1. Field of the Invention
The disclosed invention relates to a storage device.
2. Description of the Related Art
Central processing units (CPUs) have a variety of architectures depending on their usage, and an architecture called a stored-program architecture is a predominant architecture of current CPUs. In a stored-program CPU, an instruction and data needed for carrying out the instruction are stored in a semiconductor storage device (hereinafter also simply referred to as a storage device), and the instruction and the data are sequentially read from the storage device, whereby the instruction is carried out.
As the storage device, besides a main storage device for storing data and instructions, a buffer storage device called a cache which can perform data writing and data reading at high speed is given. In order to reduce access to the low-speed main storage device and speed up the arithmetic processing, a cache is provided in a CPU to be located between an arithmetic unit or a control unit and a main storage device. In general, a static random access memory (SRAM) or the like is used as a cache. Patent Document 1 shown below discloses a configuration in which a volatile memory such as an SRAM and a nonvolatile memory are used in combination as a cache.